1. Field of Invention
The present invention relates to a method for manufacturing integrated circuit. More particularly, the present invention relates to a method for manufacturing metal oxide semiconductor (MOS) device.
2. Description of Related Art
As techniques for fabricating semiconductor devices continue to develop, MOS devices having a smaller line width can be formed on a larger size wafer. Hence, integrated circuit having powerful functions is possible at a lower production cost. At present, sub-quarter-micron (0.25 .mu.m) size devices are routinely fabricated. However, as the dimensions of a device get smaller, channel length of a MOS device will also be reduced. Therefore, problems caused by having a short channel will intensify.
One common method of resolving short channel effect is to form a lightly doped region in the source/drain region of a MOS device next to the channel. This type of arrangement is referred to as forming a lightly doped drain (LDD) structure.
As dimensions of a MOS device shrink, it becomes more difficult to control the process of forming a LDD structure in the MOS device. In addition, the annealing and thermal operation operations carried out after the formation of the LDD structure can easily lead to the diffusion of ions from the lightly doped region into the substrate underneath the gate structure. Hence, a structure similar to a stacked capacitor is ultimately formed through the combination of the lightly doped drain structure in the substrate, the gate oxide layer and the gate conductive layer. When appropriate bias voltages are applied to the MOS device, a gate-to-drain capacitance (Cgd) will be developed in the area between the gate conductive layer, the gate oxide layer and the LDD region. The gate-to-drain capacitance can lead to abnormal bias and a reduction of alternating current (AC) performance of the device. Hence, the gate of the device will have a higher switching delay.
FIGS. 1A through 1C are cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming a MOS device with a lightly doped drain structure.
First, as shown in FIG. 1A, a substrate 100 having a gate structure thereon is provided. The gate structure 102 includes a gate oxide layer 104 and a gate conductive layer 106. Thereafter, using the gate structure 102 as a mask, an ion implantation 108 is carried out implanting ions into the substrate 100 to form lightly doped drain (LDD) regions 110.
Next, as shown in FIG. 1B, spacers 112 are formed on the sidewalls of the gate structure 102. In the subsequent step, using the spacers 112 and the gate structure 102 as a mask, a second ion implantation 114 is carried out implanting ions into the substrate 100. Finally, source/drain regions 116 each having a LDD region 110 are formed.
As the dimensions of a MOS device is reduced, it will be difficult to control the parameters necessary for forming a LDD region 110 inside a source/drain region 116. In addition, subsequent thermal annealing operations may be required. Due to the diffusion of ions from the LDD region 110 into the substrate 100 underneath the gate structure 102 (region 118 in FIG. 1C), a structure similar to a capacitor is formed. The capacitor structure is formed through the combination of the LDD region 110, the gate oxide layer 104 and the gate conductive layer 106. When appropriate bias voltages are applied to the MOS device, a gate-to-drain capacitance (Cgd) will be developed in the area between the gate conductive layer 106, the gate oxide layer 104 and the region 118. The gate-to-drain capacitance can lead to abnormal bias and a reduction of alternating current (AC) performance of the device. Hence, the gate 102 will have a higher switching delay.
To reduce the gate-to-drain capacitance (Cgd), offset spacers each having a thickness of about 0.015 .mu.m is formed on the sidewalls of the gate structure prior to the implantation of ions into the substrate to form the LDD structure. The offset spacers can prevent the over-diffusion of ions from the LDD region into neighboring substrate region underneath the gate structure. Hence, the gate-to-drain capacitance resulting from the gate conductive layer, the gate oxide layer and the source/drain region can be eliminated.
FIGS. 2A through 2C are cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming a MOS device with offset spacers on the sidewalls of a gate structure.
First, as shown in FIG. 2A, a substrate 200 is provided. Then, a gate structure 202 is formed over the substrate 200. The gate structure 202 includes a gate oxide 20 layer 204 and a gate conductive layer 206. The gate structure has a cross-sectional width 207 of about 0.25 .mu.m. Thereafter, a thin oxide annealing operation 208 is carried out to anneal the substrate 200 and the gate structure 202 at a temperature of about 800.degree. C. Consequently, any crystal defects on the substrate 200 surface and within the gate structure 202 will be cleared away due to the re-crystallization of internal lattice structure. However, because of the high-temperature annealing operation, bird's beaks will form at the interface between the gate oxide layer 204 and the gate conductive layer 206.
Next, as shown in FIG. 2B, offset spacers 210 are formed on the sidewalls of the gate structure 202. The offset spacer can be a silicon dioxide layer having a thickness 211 of about 0.015 .mu.m.
Next, as shown in FIG. 2C, using the gate structure 202 and the offset spacers 210 as a mask, an ion implantation is carried out implanting ions into the substrate to form lightly doped drain region 212. Thereafter, another spacers 214 are formed on the exterior sidewalls of the offset spacers 210. Finally, using the gate structure 202, the offset spacers 210 and the spacers 214 as a mask, a second ion implantation is carried out implanting ions into the substrate 200 to form source/drain regions 216.
Since the ion implantation operation for forming the LDD region 212 is performed only after the offset spacers 210 are formed, ionic diffusion from the LDD region 212 to the substrate will be buffered by the offset spacer. In other words, the ions in the LDD region 212 have to diffuse across the entire thickness of the offset spacer before reaching the substrate 200 underneath the gate structure 202. Therefore, the number of ions capable of diffusing into the substrate underneath the gate structure 202 is reduced considerably. The reduction of ions in that area will minimize the gate20 to-drain capacitance established through the combination of gate conductive layer 206, the gate oxide layer 204 and the source/drain region 216.
However, bird' beaks 218 are formed at the interface between the gate conductive layer 206 and the gate oxide layer 204 due to the thin oxide annealing operation at about 800.degree. C. The presence of bird's beaks 218 will make the thickness of the gate oxide layer 204 highly irregular and resulting in a change in threshold voltage of the device. Hence, the gate-to-drain capacitance (Cgd) formed by the gate conductive layer, the gate oxide layer and the channel region will be unstable. consequently, the switching delay of each gate will vary leading to poor device quality.
In addition, each offset spacer 210 has a thickness of about 0.015 .mu.m (as shown in FIG. 2B), and that offset spacers 210 are formed on each side of the gate structure 202. Since the gate structure 202 has a width of about 0.25 .mu.m, the overall with of the final gate structure is about 0.28 .mu.m. Hence, the addition of the offset spacers 210 will tend to increase the channel region 220 (as shown in FIG. 2C) underneath the gate structure 202 from 0.25 .mu.m to 0.28 .mu.m. Because a longer channel length will have a higher resistance, there will be a reduction in potential current flowing through the channel. Consequently, efficiency of the device will be lowered.
In light of the foregoing, there is a need to provide an improved method for forming MOS device.